1. Field of the Invention
This invention relates to compilers and instruction scheduling, and particularly to systems, methods and computer products for compiler support for aggressive safe load speculation.
2. Description of Background
Modern microprocessors are generally designed with deep computing pipelines. For this reason, special techniques are needed to more fully utilize chip resources. One such technique is speculative execution. For example, for code such as:
while (*p != ‘s’)p++;
for which the corresponding machine code is generated is:
CL.3:AIgr3=gr3,1LIZgr0,gr4=(*)uchar(gr4,0)C4cr0=gr0,115BFCL.3,cr0,0×4/eq ,taken=80%(80,20)
There are several delay cycles in the sequence of load, compare and branch instructions. The amount of delay depends on the particular microprocessor. For example, certain machines have three delay cycles from a load instruction to a compare instruction, and three delay cycles from a compare instruction to a branch instruction.
Simply unrolling a loop such as:
CL.52:LIZUgr0,gr3=(*)uchar(gr3,1)C4cr0=gr0,115BTCL.6,cr0,0×4/eq ,taken=20%(20,80)LIZUgr0,gr3=(*)uchar(gr3,1)C4cr0=gr0,115BTCL.6,cr0,0×4/eq ,taken=20%(20,80)LIZUgr0,gr3=(*)uchar(gr3,1)C4cr0=gr0,115BTCL.6,cr0,0×4/eq ,taken=20%(20,80)LIZUgr0,gr3=(*)uchar(gr3,1)C4cr0=gr0,115BFCL.52,cr0,0×4/eq ,taken=80%(80,20)CL.6:cannot improve the performance since load instructions cannot usually be safely reordered with branch instructions. Otherwise a violation exception may occur at run time.
What is needed is a compiler to perform aggressive load speculation safely.